The continuing improvements in semiconductor integrated circuit technology have resulted in the capability of forming increased numbers of transistors, resistors, etc., within a given semiconductor chip. For example, the advent of ion implantation has allowed devices to be smaller and improved masking and isolation techniques have allowed devices to be more closely spaced. This overall miniaturization effect has resulted in decreased cost and improved performance in integrated circuits. Unfortunately, though, many of the devices formed within the semiconductor chip must remain unused in the completed chip because of the lack of available space for wiring all of the circuits together.
For example, a practical state of the art integrated circuit chip containing between 700-2,000 circuits typically utilizes less than 50% of the available circuits. The principle reason for this is the inadequate space available on the surface of the chip for wiring all of the circuits. The interconnection metallurgy system atop the chip is extremely complex and bulky, requiring the spacing between the wires to be very tight. To achieve even a 50% efficiency of circuit utilization, at least 2 or 3 and possibly 4 separate levels of complex conductive wiring patterns, each separated by one or more layers of dielectric material, are used.
One solution to solving the above mentioned interconnection wiring problem is found in advanced bipolar semiconductor products, wherein metal studs are employed to provide contact between circuit components and their interconnect wiring. These metal studs are essential for efficient utilization of chip real estate and in maintaining a planar wiring structure essential for both high performance and reliability. The relatively small diameter and large height of the contact stud, however, imposes particular problems and therefore limits the number of methods suitable for their construction. A prior technique for forming metal studs of this nature is disclosed in commonly owned U.S. Pat. No. 4,410,622 (Dalal, et al.). FIGS. 1A-1D provide a simplified illustration of the method for forming metal contact studs atop a semiconductor substrate according to Dalal et al. First, a polyether sulfone layer is deposited on top of the substrate, followed by the deposition of an organic polymer material such as a novolak resin based (NVR) positive resist. The NVR layer is then baked to 210.degree. C.-230.degree. C. to render it photoinsensitive. A photosensitive resist layer is then deposited on the NVR layer, and a pattern is transferred to the substrate by exposing the pattern through the photoresist material and then etching through the NVR and the polyether sulfone layer. Dalal, et al. discloses leaving the entire polyether sulfone layer intact, although it is desirable to have a pattern which is etched to the semiconductor substrate. Blanket deposition of a metallization layer thereby leaves a metallic stud deposited on top of the semiconductor substrate. Removal of the metallization, NVR, photoresist, and metallization layer is accomplished by dissolving the polyether sulfone layer using N-methylpyrrolidone (NMP) or other suitable solvent, thereby quickly lifting off these layers and leaving only the metal stud deposited on the substrate.
Referring now to FIG. 1A, the prior method for depositing metal studs includes the initial step of depositing a polyether sulfone layer 12 onto a semiconductor substrate 10. A novolak resin based positive resist layer 14 is then deposited onto the polyether sulfone layer 12. The positive resist layer 14 is then baked at a temperature range of about 210.degree. C. to 230.degree. C. in order to render it photo insensitive. Atop the resist layer 14 is deposited a photosensitive resist layer 16.
Referring now to FIG. 1B, the resist layer 16 is subjected to radiation and is developed in a manner well known in the prior art, to thereby provide a relief pattern image 18. The resist mask is then used to facilitate selective removal of the underlying layers 14 and 12 to expose a window 20 therein. It is to be noted that there may be millions of such windows formed atop the semiconductor substrate 10. Window 20 is merely exemplary of one such window. The technique of forming the windows and layers 14 and 12 is well known in the prior art.
Referring now to FIG. lC, after the window 20 is formed, a metal layer 22 is blanket deposited over the entire structure, thereby forming a metal stud 24 onto semiconductor substrate 10 in window 20.
Referring now to FIG. 1D, the layers 14, 16, 22 are then quickly lifted off by using NMP or another suitable solvent to dissolve and release the polyether sulfone layer 12, thereby leaving the pattern metal stud 24 adhered to the surface of the semiconductor substrate 10. During the lift-off process, residue polyether sulfone (not shown) might remain and can be removed by dissolving it in a suitable solvent, such as NMP, in an additional step.
This method is unsuitable, however, because during the lift-off process the studs are damaged from the impact of the lift-off layers 12, 14, 16 and 22. One of the damage conditions is referred to as "tilted stud" and is illustrated in FIG. 1D. With this condition, the stud is still able to make electrical connection. However, the area of electrical connection is significantly reduced, thereby leading to a potentially unreliable connection some time in the future, when repairing such a defect or replacing the part is extremely expensive. It is evident from FIGS. 1A-1D that the lift-off structure has significantly more mass than the studs.
Dalal et al. therefore provides a method of forming metal studs by utilizing the sensitivity of a polyether sulfone underlay, which is first deposited onto the substrate, to NMP. This process is unacceptable for the smaller semiconductor structures utilized at the present time, however, because damage occurs to the studs during the lift off process. This is due to the fact that the studs comprise only a small percentage of the overall area of the substrate, with the structure which is lifted off taking up the remaining area. As a result, the structure comprising the polyether sulfone, NVR, photoresist and metallization layer collides with the metal studs during the lift off process, thereby causing impact damage to the studs. It is to be noted that damage to even a single metal structure is a potential reliability problem which warrants rejection of an entire chip.
A method of producing undamaged, reliable metallurgy which overcomes the deficiencies of the prior art, is therefore, highly desirable.